Electronic component modules containing multiple IC packages have come into common use. The IC devices contained within such packages often generate sufficient heat to require thermal management. The objective of thermal management in the design of electronic component packaging is to maintain the operating temperature of the active circuit or junction side of the devices low enough to prevent premature component failure. A typical approach to the thermal management of multiple IC packages is to utilize a single heat sink in heat transfer relationship with the upper surfaces of the module's IC packages for dissipating the heat generated into the ambient environment. A single heat sink common to all of the IC packages reduces the number of parts and space required as well as the cost of the module, and increases the total surface area available for transferring heat to the surroundings.
For high power IC devices such as microprocessors, large gate arrays and application-specific integrated circuits (ASICs) that generate significant amounts of thermal energy during operation, the use of a heat sink requires that a low thermal impedance interface exist between the upper surfaces of the IC packages and the heat sink. The efficiency of the thermal interface between the IC packages of a multi-package module and the associated single heat sink may be compromised, however, because of physical variations between the IC packages within the module. These variations are difficult, if not impossible, to avoid in a standard manufacturing process which allows for dimensional tolerances in each of the components of the package. In a package comprising stacked components, the tolerances are additive so that it is not unusual for there to be significant variations, for example, 0.015-0.020 inch, in the overall heights of the IC packages within a given module. These differences introduce non-coplanarities and gaps that can substantially reduce the efficiency of heat transfer across the heat sink/IC package interface.
Non-coplanarity of the upper surfaces of a module's multiple IC packages may also result from the particular interconnect system that is used. For example, although various interconnect options are available including those in which terminated IC devices are soldered to pads on a substrate, it is often advantageous to insert each IC device in a socket as opposed to permanently soldering it fast. In pin grid array (PGA) interconnect systems the socket is soldered to the substrate. The costly IC devices may thus be easily removed and upgraded, with the replaced IC device being salvageable. However, the process of attaching a socket to the substrate can result in slight deviations in the placement of the socket from a nominal position on the component surface of the substrate. For example, the soldered socket may be tilted relative to the substrate's component surface or, although parallel with the component surface, the socket may be soldered in a position that is somewhat higher than nominal. In any case, these positional deviations further contribute to the non-coplanarity of the upper, heat sink-confronting surfaces of the IC devices inserted in the sockets with a concomitant reduction in heat transfer efficiency.
Various approaches have been developed for addressing the problem of non-coplanarity of the upper surfaces of the IC packages in multiple IC package modules.
For example, in one approach, disclosed in U.S. Pat. Ser. No. 5,323,292 issued Jun. 21, 1994, to Brzezinski and assigned to the owner of the present invention, interposed between the multiple IC packages and an associated heat sink is a volume of liquid within a fluid-tight chamber. The volume of liquid interacts with a deformable membrane forming a wall of the chamber, the membrane being engaged by the non-coplanar surfaces of the multiple IC packages. The membrane serves as a conformal interface that compensates for variations in the heights and mounting angles of the IC devices within the package. Although providing a satisfactory solution, this approach tends to be complex and expensive.
Compensation for the non-coplanarity of multiple IC packages within a module has also been attempted by using a separate heat sink for each IC package. However, this expedient nullifies the many advantages, outlined earlier, of using a single heat sink.
In another known approach to the problem, a thick, compliant, thermally conductive layer is interposed between the upper surfaces of the IC devices and a single heat sink to compensate for device height variations. However, such thick interface materials provide very poor thermal performance compared to the highly efficient, thin interfaces mentioned above.